155 search results - page 1 / 31 » Reducing Design Complexity of the Load Store Queue |
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
With faster CPU clocks and wider pipelines, all relevant microarchitecture components should scale accordingly. There have been many proposals for scaling the issue queue, registe...
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
High-performance processors use a large set–associative L1 data cache with multiple ports. As clock speeds and size increase such a cache consumes a significant percentage of t...
HPCA
2005
IEEE
14 years 5 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
ISCA
2005
IEEE
13 years 10 months ago
2005
IEEE
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
MICRO
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents NoSQ (short for No Store Queue), a microarchitecture that performs store-load communication without a store queue and without executing stores in the outof-ord...