14 search results - page 1 / 3 » Reducing Memory Latency via Read-after-Read Memory Dependenc... |
MICRO
1999
IEEE
13 years 9 months ago
1999
IEEE
: We identify that typical programs exhibit highly regular read-after-read (RAR) memory dependence streams. We exploit this regularity by introducing read-after-read (RAR) memory d...
TC
2002
13 years 4 months ago
2002
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
We revisit memory hierarchy design viewing memory as an inter-operation communication agent. This perspective leads to the development of novel methods of performing inter-operati...
ICS
2005
Tsinghua U.
13 years 10 months ago
2005
Tsinghua U.
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
ASPLOS
2004
ACM
13 years 10 months ago
2004
ACM
This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. ...