12 search results - page 2 / 3 » Reducing Operand Transport Complexity of Superscalar Process... |
HPCA
2006
IEEE
14 years 5 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
CJ
2006
13 years 5 months ago
2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission ...
HPCA
1998
IEEE
13 years 9 months ago
1998
IEEE
A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pi...
JCIT
2007
13 years 5 months ago
2007
Queue computers are a viable option for embedded systems design. Queue computers feature a dense instruction set, high parallelism, low hardware complexity. In this paper we propo...