40 search results - page 1 / 8 » Reducing cache misses through programmable decoders |
TACO
2008
13 years 5 months ago
2008
ISCA
2006
IEEE
13 years 11 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
VALUETOOLS
2006
ACM
13 years 11 months ago
2006
ACM
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Modern embedded CPU systems rely on a growing number of software features, but this growth increases the memory footprint and increases the need for efficient instruction and data...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
Vertex cache of programmable geometry processor The proposed architecture of vertex cache is divided into is proposed and implemented. The proposed vertex cache is pre-TnL vertex c...