88 search results - page 3 / 18 » Reducing energy and delay using efficient victim caches |
ASPDAC
2004
ACM
13 years 9 months ago
2004
ACM
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
HPCA
2006
IEEE
13 years 11 months ago
2006
IEEE
Caches are very inefficiently utilized because not all the excess data fetched into the cache, to exploit spatial locality, is utilized. We define cache utilization as the percent...
ARCS
2006
Springer
13 years 9 months ago
2006
Springer
As applications tend to grow more complex and use more memory, the demand for cache space increases. Thus embedded processors are inclined to use larger caches. Predicting a miss i...
DATE
2004
IEEE
13 years 9 months ago
2004
IEEE
In the context of portable embedded systems, reducing energy is one of the prime objectives. Most high-end embedded microprocessors include onchip instruction and data caches, alo...
IPCCC
2006
IEEE
13 years 11 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...