49 search results - page 10 / 10 » Reduction of Power Dissipation during Scan Testing by Test V... |
ITC
1999
IEEE
13 years 9 months ago
1999
IEEE
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture a...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
PATMOS
2000
Springer
13 years 9 months ago
2000
Springer
Abstract. Reduction of chip packaging and cooling costs for deep sub-micron SystemOn-Chip (SOC) designs is an emerging issue. We present a simulation-based methodology able to real...
MICCAI
2006
Springer
14 years 6 months ago
2006
Springer
Although magnetic resonance imaging is considered to be non-invasive, there is at least one effect on the patient which has to be monitored: The heating which is generated by absor...