73 search results - page 15 / 15 » Reduction of interpolants for logic synthesis |
MSE
1999
IEEE
13 years 10 months ago
1999
IEEE
Intellectual property IP blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time ...
ASAP
2009
IEEE
13 years 9 months ago
2009
IEEE
An implementation of a radix-4 approximate squaring circuit is described employing a new operand dual recoding technique. Approximate squaring circuits have numerous applications ...
CODES
2008
IEEE
14 years 20 days ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...