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HPCA
1999
IEEE
13 years 9 months ago
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
ISCAS
2006
IEEE
157views Hardware» more  ISCAS 2006»
13 years 11 months ago
DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...
Daewook Kim, Manho Kim, Gerald E. Sobelman
JPDC
2006
92views more  JPDC 2006»
13 years 5 months ago
A tight bound on remote reference time complexity of mutual exclusion in the read-modify-write model
In distributed shared memory multiprocessors, remote memory references generate processor-to-memory traffic, which may result in a bottleneck. It is therefore important to design ...
Sheng-Hsiung Chen, Ting-Lu Huang
DSD
2006
IEEE
174views Hardware» more  DSD 2006»
13 years 8 months ago
Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering
Title of thesis: Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering Alokika Dash, Master of Science, 2006 Thesis dire...
Alokika Dash, Peter Petrov
ICPP
1994
IEEE
13 years 9 months ago
An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors
Both hardware and software prefetching have been shown to be e ective in tolerating the large memory latencies inherent in shared-memory multiprocessors however, both types of pre...
Edward H. Gornish, Alexander V. Veidenbaum