35 search results - page 2 / 7 » Register Allocation Via Coloring of Chordal Graphs |
LCPC
2005
Springer
13 years 10 months ago
2005
Springer
Techniques for global register allocation via graph coloring have been extensively studied and widely implemented in compiler frameworks. This paper examines a particular variant ...
ICCAD
2007
IEEE
2007
IEEE
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
14 years 1 months ago
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...
CGO
2007
IEEE
13 years 11 months ago
2007
IEEE
Memory transfers are becoming more important to optimize, for both performance and power consumption. With this goal in mind, new register allocation schemes are developed, which ...
ESOP
2010
Springer
14 years 2 months ago
2010
Springer
Iterated Register Coalescing (IRC) is a widely used heuristic for performing register allocation via graph coloring. Many implementations in existing compilers follow (more or less...
ECRTS
2007
IEEE
13 years 11 months ago
2007
IEEE
Conventionally, the use of virtual memory in real-time systems has been avoided, the main reason being the difficulties it provides to timing analysis. However, there is a trend ...