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» Register Allocation Via Coloring of Chordal Graphs
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IEEEPACT
2002
IEEE
13 years 9 months ago
A Framework for Parallelizing Load/Stores on Embedded Processors
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
Xiaotong Zhuang, Santosh Pande, John S. Greenland ...
ISSS
1996
IEEE
103views Hardware» more  ISSS 1996»
13 years 9 months ago
Instruction Set Design and Optimizations for Address Computation in DSP Architectures
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instructio...
Guido Araujo, Ashok Sudarsanam, Sharad Malik
ICASSP
2011
IEEE
12 years 8 months ago
Multi-graph regularization for efficient delivery of user generated content in online social networks
We present a methodology for enhancing the delivery of usergenerated content in online social networks. To this end, we first regularize the social graph via node capacity and li...
Jacob Chakareski
PLDI
2003
ACM
13 years 10 months ago
Static array storage optimization in MATLAB
An adaptation of the classic register allocation algorithm to the problem of array storage optimization in MATLAB is presented. The method involves the decomposition of an interfe...
Pramod G. Joisha, Prithviraj Banerjee
ICC
2009
IEEE
157views Communications» more  ICC 2009»
13 years 11 months ago
A Graph Approach to Dynamic Fractional Frequency Reuse (FFR) in Multi-Cell OFDMA Networks
A graph-based framework for dynamic fractional frequency reuse (FFR) in multi-cell OFDMA networks is proposed in this work. FFR is a promising resource allocation technique that c...
Ronald Chang, Zhifeng Tao, Jinyun Zhang, C.-C. Jay...