32 search results - page 2 / 7 » Register File Design Considerations in Dynamically Scheduled... |
ISCA
1997
IEEE
13 years 9 months ago
1997
IEEE
LCTRTS
2007
Springer
13 years 11 months ago
2007
Springer
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in desig...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
— We propose a low-leakage register file cell design based on the observation that the physical registers in a superscalar processor have very short life cycles. When a register...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
ASPLOS
2004
ACM
13 years 10 months ago
2004
ACM
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...