14 search results - page 1 / 3 » Register Sharing Verification During Data-Path Synthesis |
ICCTA
2007
IEEE
13 years 8 months ago
2007
IEEE
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
A control part ? data path partition based sequential circuit verification scheme aimed at avoiding state explosion comprises two major modules namely, a data path verifier and a ...
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
Orthogonal scan paths, which follow the path of the data flow, can be used in data path designs to reduce the test overhead -- area, delay and test application time -- by sharing ...
ASAP
2007
IEEE
13 years 6 months ago
2007
IEEE
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
DATE
1999
IEEE
1999
IEEE
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
13 years 9 months ago
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...