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CC
1998
Springer
125views System Software» more  CC 1998»
13 years 9 months ago
A New Fast Algorithm for Optimal Register Allocation in Modulo Scheduled Loops
Sylvain Lelait, Guang R. Gao, Christine Eisenbeis
MICRO
1992
IEEE
133views Hardware» more  MICRO 1992»
13 years 9 months ago
Code generation schema for modulo scheduled loops
Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. Modulo scheduling i...
B. Ramakrishna Rau, Michael S. Schlansker, Parthas...
IPPS
1998
IEEE
13 years 10 months ago
Register-Sensitive Software Pipelining
In this paper, we propose an integrated approach for register-sensitive software pipelining. In this approach, the heuristics proposed in the stage scheduling method of Eichenberg...
Amod K. Dani, V. Janaki Ramanan, Ramaswamy Govinda...
ICCAD
2001
IEEE
184views Hardware» more  ICCAD 2001»
14 years 2 months ago
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
Cagdas Akturan, Margarida F. Jacome
ISSS
2002
IEEE
154views Hardware» more  ISSS 2002»
13 years 10 months ago
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...
Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edw...