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FPGA
1995
ACM
120views FPGA» more  FPGA 1995»
13 years 8 months ago
Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses
A novel approach is presented for transforming a given scheduled and bound signal processing algorithm for a multiplexer based datapath to a BUS/RAM based FPGA datapath. A datapat...
Baher Haroun, Behzad Sajjadi
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
13 years 10 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
DAC
2004
ACM
14 years 6 months ago
Memory access scheduling and binding considering energy minimization in multi-bank memory systems
Memory-related activity is one of the major sources of energy consumption in embedded systems. Many types of memories used in embedded systems allow multiple operating modes (e.g....
Chun-Gi Lyuh, Taewhan Kim
DATE
2010
IEEE
193views Hardware» more  DATE 2010»
13 years 10 months ago
Coordinated resource optimization in behavioral synthesis
Abstract—Reducing resource usage is one of the most important optimization objectives in behavioral synthesis due to its direct impact on power, performance and cost. The datapat...
Jason Cong, Bin Liu, Junjuan Xu
ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
14 years 2 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha