76 search results - page 3 / 16 » Register placement for low power clock network |
DAC
2005
ACM
13 years 7 months ago
2005
ACM
Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of th...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
— A methodology based on supply voltage optimization for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in th...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
- The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were...
CODES
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
FPL
2007
Springer
13 years 11 months ago
2007
Springer
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...