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» Regular layout generation of logically optimized datapaths
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FPGA
2008
ACM
174views FPGA» more  FPGA 2008»
13 years 7 months ago
Pattern-based behavior synthesis for FPGA resource reduction
Pattern-based synthesis has drawn wide interest from researchers who tried to utilize the regularity in applications for design optimizations. In this paper we present a general p...
Jason Cong, Wei Jiang
ARITH
2003
IEEE
13 years 11 months ago
High-Performance Left-to-Right Array Multiplier Design
We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed de...
Zhijun Huang, Milos D. Ercegovac
ASPDAC
2011
ACM
297views Hardware» more  ASPDAC 2011»
12 years 9 months ago
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits
3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequent...
Shashikanth Bobba, Ashutosh Chakraborty, Olivier T...
SIGMOD
2000
ACM
236views Database» more  SIGMOD 2000»
13 years 10 months ago
XTRACT: A System for Extracting Document Type Descriptors from XML Documents
XML is rapidly emerging as the new standard for data representation and exchange on the Web. An XML document can be accompanied by a Document Type Descriptor (DTD) which plays the...
Minos N. Garofalakis, Aristides Gionis, Rajeev Ras...
POPL
2004
ACM
14 years 6 months ago
Incremental execution of transformation specifications
We aim to specify program transformations in a declarative style, and then to generate executable program transformers from such specifications. Many transformations require non-t...
Ganesh Sittampalam, Oege de Moor, Ken Friis Larsen