1179 search results - page 2 / 236 » Relative Timing Based Verification of Timed Circuits and Sys... |
DAC
1999
ACM
14 years 6 months ago
1999
ACM
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
CAV
2001
Springer
13 years 10 months ago
2001
Springer
DAC
1990
ACM
13 years 9 months ago
1990
ACM
In this paper, we provide an overview of a system designed for verifying the consistency of timing specifications for digital circuits. The utility of the system comes from the ne...
ASPDAC
2010
ACM
13 years 3 months ago
2010
ACM
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...