6 search results - page 1 / 2 » Relaxed Simulated Tempering for VLSI Floorplan Designs |
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
In the past two decades, the simulated annealing technique has been considered as a powerful approach to handle many NP-hard optimization problems in VLSI designs. Recently, a new...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
As the size and complexity of VLSI circuits increase, the need for faster floorplanning algorithms also grows. In this work we introduce Traffic, a new method for creating wire- a...
ASPDAC
2000
ACM
13 years 9 months ago
2000
ACM
Simulated annealing has been one of the most popular stochastic optimization methods used in the VLSI CAD field in the past two decades for handling NP-hard optimization problems...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
As technology advances, the metal width is decreasing with the length increasing, making the resistance along the power line increase substantially. Together with the nonlinear sc...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-sca...