37 search results - page 1 / 8 » Reliability evaluation of combinational logic circuits by sy... |
VTS
1995
IEEE
13 years 8 months ago
1995
IEEE
DAC
1990
ACM
13 years 9 months ago
1990
ACM
Symbolic simulation involves evaluating circuit behavior using special symbolic values to encode a range of circuit operating conditions. In one simulation run, a symbolic simulat...
ICCAD
1991
IEEE
13 years 8 months ago
1991
IEEE
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on ...