3 search results - page 1 / 1 » Reliability-Constrained Area Optimization of VLSI Power Grou... |
DAC
1999
ACM
14 years 5 months ago
1999
ACM
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
— In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linea...
INTEGRATION
2007
13 years 4 months ago
2007
In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear p...