74 search results - page 15 / 15 » Reordering Algorithm for Minimizing Test Power in VLSI Circu... |
FCCM
1999
IEEE
13 years 9 months ago
1999
IEEE
The time it takes to reconfigure FPGAs can be a significant overhead for reconfigurable computing. In this paper we develop new compression algorithms for FPGA configurations that...
CODES
2005
IEEE
13 years 11 months ago
2005
IEEE
Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom de...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...