14 search results - page 2 / 3 » Reordering Memory Bus Transactions for Reduced Power Consump... |
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
ICS
2005
Tsinghua U.
13 years 10 months ago
2005
Tsinghua U.
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
VLSID
2009
IEEE
14 years 5 months ago
2009
IEEE
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
DSD
2006
IEEE
13 years 8 months ago
2006
IEEE
Title of thesis: Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering Alokika Dash, Master of Science, 2006 Thesis dire...
CODES
2011
IEEE
12 years 4 months ago
2011
IEEE
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...