Sciweavers

38 search results - page 2 / 8
» Representing Product Designs Using a Description Graph Exten...
Sort
View
FROCOS
2011
Springer
12 years 4 months ago
Tailoring Temporal Description Logics for Reasoning over Temporal Conceptual Models
Temporal data models have been used to describe how data can evolve in the context of temporal databases. Both the Extended Entity-Relationship (EER) model and the Unified Modelli...
Alessandro Artale, Roman Kontchakov, Vladislav Ryz...
DFG
2004
Springer
13 years 8 months ago
Modeling and Formal Verification of Production Automation Systems
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wo...
VLSID
2004
IEEE
292views VLSI» more  VLSID 2004»
14 years 5 months ago
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
Jeremy Chan, Sri Parameswaran
BMCBI
2006
115views more  BMCBI 2006»
13 years 4 months ago
MitoRes: a resource of nuclear-encoded mitochondrial genes and their products in Metazoa
Background: Mitochondria are sub-cellular organelles that have a central role in energy production and in other metabolic pathways of all eukaryotic respiring cells. In the last f...
Domenico Catalano, Flavio Licciulli, Antonio Turi,...
ATVA
2009
Springer
141views Hardware» more  ATVA 2009»
13 years 9 months ago
Formal Verification for High-Assurance Behavioral Synthesis
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Ya...