133 search results - page 2 / 27 » Resilient design in scaled CMOS for energy efficiency |
DAC
2003
ACM
14 years 7 months ago
2003
ACM
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
ICCD
2007
IEEE
14 years 3 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
ISVLSI
2008
IEEE
14 years 20 days ago
2008
IEEE
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
CASES
2006
ACM
13 years 10 months ago
2006
ACM
Probabilistic arithmetic, where the ith output bit of addition and multiplication is correct with a probability pi, is shown to be a vehicle for realizing extremely energy-efficie...
ISVLSI
2002
IEEE
13 years 11 months ago
2002
IEEE
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...