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» Resource Sharing in Custom Instruction Set Extensions
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SASP
2008
IEEE
77views Hardware» more  SASP 2008»
13 years 11 months ago
Resource Sharing in Custom Instruction Set Extensions
Abstract—Customised processor performance generally increases as additional custom instructions are added. However, performance is not the only metric that modern systems must ta...
Marcela Zuluaga, Nigel P. Topham
DATE
2006
IEEE
112views Hardware» more  DATE 2006»
13 years 10 months ago
Automating processor customisation: optimised memory access and resource sharing
We propose a novel methodology to generate Application Specific Instruction Processors (ASIPs) including custom instructions. Our implementation balances performance and area req...
Robert G. Dimond, Oskar Mencer, Wayne Luk
SASP
2009
IEEE
156views Hardware» more  SASP 2009»
13 years 11 months ago
Introducing control-flow inclusion to support pipelining in custom instruction set extensions
—Multi-cycle Instruction set extensions (ISE) can be pipelined in order to increase their throughput; however, typical program traces seldom contain consecutive calls to the same...
Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel ...
CASES
2004
ACM
13 years 8 months ago
Scalable custom instructions identification for instruction-set extensible processors
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. However, it is computationally expensive to automaticall...
Pan Yu, Tulika Mitra
DAC
2004
ACM
13 years 10 months ago
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
Philip Brisk, Adam Kaplan, Majid Sarrafzadeh