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» Retargetable compilation for low power
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EMSOFT
2005
Springer
13 years 11 months ago
Using de-optimization to re-optimize code
The nature of embedded systems development places a great deal of importance on meeting strict requirements in areas such as static code size, power consumption, and execution tim...
Stephen Hines, Prasad Kulkarni, David B. Whalley, ...
CGO
2004
IEEE
13 years 9 months ago
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv...
SENSYS
2009
ACM
14 years 16 days ago
Evaluating a BASIC approach to sensor network node programming
Sensor networks have the potential to empower domain experts from a wide range of fields. However, presently they are notoriously difficult for these domain experts to program, ...
J. Scott Miller, Peter A. Dinda, Robert P. Dick
CODES
2008
IEEE
14 years 6 days ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava
ISCAPDCS
2007
13 years 7 months ago
Evaluation of architectural support for speech codecs application in large-scale parallel machines
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
Naeem Zafar Azeemi