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» Retiming Finite State Machines to Control Hardened Data-Path...
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SBCCI
2003
ACM
84views VLSI» more  SBCCI 2003»
13 years 10 months ago
Retiming Finite State Machines to Control Hardened Data-Paths
Ivan Augé, François Donnet, Fr&eacut...
ICCTA
2007
IEEE
13 years 8 months ago
Register Sharing Verification During Data-Path Synthesis
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sa...
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 1 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...