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» Retiming for Synchronous Data Flow Graphs
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ASPDAC
2007
ACM
93views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Retiming for Synchronous Data Flow Graphs
Nikolaos D. Liveris, Chuan Lin, J. Wang, Hai Zhou,...
ISCAPDCS
2001
13 years 7 months ago
On Retiming Synchronous Data-Flow Graphs
Timothy W. O'Neil, Edwin Hsing-Mean Sha
DAM
2008
72views more  DAM 2008»
13 years 5 months ago
Minimization of circuit registers: Retiming revisited
In this paper, we address the following problem: given a synchronous digital circuit, is it possible to construct a new circuit computing the same function as the original one but...
Bruno Gaujal, Jean Mairesse
ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
13 years 10 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
ASPDAC
2011
ACM
227views Hardware» more  ASPDAC 2011»
12 years 9 months ago
Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph
– This paper concerns throughput-constrained parallel execution of synchronous data flow graphs. This paper assumes static mapping and dynamic scheduling of nodes, which has seve...
Tae-ho Shin, Hyunok Oh, Soonhoi Ha