22 search results - page 1 / 5 » Return Address Protection on Cache Memories |
IEICET
2006
13 years 4 months ago
2006
ICS
2009
Tsinghua U.
13 years 11 months ago
2009
Tsinghua U.
The speed gap between processor and memory continues to limit performance. To address this problem, we explore the potential of eliminating Zero Loads—loads accessing memory loc...
OTM
2004
Springer
13 years 10 months ago
2004
Springer
Cache memories are mandatory to bridge the growing gap between CPU speed and main memory access time. Standard cache organizations improve the average execution time but are diffi...
ACSAC
2009
IEEE
13 years 11 months ago
2009
IEEE
—To strengthen systems against code injection attacks, the write or execute only policy (W⊕X) and address space layout randomization (ASLR) are typically used in combination. T...
ISCA
2009
IEEE
13 years 11 months ago
2009
IEEE
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...