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DATE
2003
IEEE
141views Hardware» more  DATE 2003»
13 years 11 months ago
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
Mahesh Mamidipaka, Nikil D. Dutt
PAM
2009
Springer
14 years 23 days ago
Revisiting Route Caching: The World Should Be Flat
Internet routers’ forwarding tables (FIBs), which must be stored in expensive fast memory for high-speed packet forwarding, are growing quickly in size due to increased multihomi...
Changhoon Kim, Matthew Caesar, Alexandre Gerber, J...
SPAA
1998
ACM
13 years 10 months ago
Lamport Clocks: Verifying a Directory Cache-Coherence Protocol
Modern shared-memory multiprocessors use complex memory system implementations that include a variety of non-trivial and interacting optimizations. More time is spent in verifying...
Manoj Plakal, Daniel J. Sorin, Anne Condon, Mark D...
ISCA
2010
IEEE
305views Hardware» more  ISCA 2010»
13 years 11 months ago
Rethinking DRAM design and organization for energy-constrained multi-cores
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
Aniruddha N. Udipi, Naveen Muralimanohar, Niladris...
VTS
2007
IEEE
203views Hardware» more  VTS 2007»
14 years 8 days ago
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code
Conventional error correcting code (ECC) schemes used in memories and caches cannot correct double bit errors caused by a single event upset (SEU). As memory density increases, mu...
Avijit Dutta, Nur A. Touba