287 search results - page 58 / 58 » Reversible logic circuit synthesis |
CODES
2008
IEEE
14 years 7 days ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
LCTRTS
2010
Springer
13 years 3 months ago
2010
Springer
Concurrent Action-Oriented Specifications (CAOS) model the behavior of a synchronous hardware circuit as asynchronous guarded at an abstraction level higher than the Register Tran...