768 search results - page 3 / 154 » Robustness of Sequential Circuits |
DAC
1994
ACM
13 years 10 months ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
ICCD
2006
IEEE
13 years 11 months ago
2006
IEEE
—This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose t...
ICCAD
2007
IEEE
14 years 2 months ago
2007
IEEE
Retiming and resynthesis are among the most important techniques for practical sequential circuit optimization. However, their applicability is much limited due to verification c...
ISLPED
1997
ACM
13 years 9 months ago
1997
ACM
A new statistical technique for average power estimation in sequential circuits is presented. Due to the feedback mechanism, conventional statistical procedures cannot be applied ...
FPGA
1997
ACM
13 years 10 months ago
1997
ACM
Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the ...