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ISCA
2007
IEEE
145views Hardware» more  ISCA 2007»
13 years 11 months ago
Mechanisms for store-wait-free multiprocessors
Store misses cause significant delays in shared-memory multiprocessors because of limited store buffering and ordering constraints required for proper synchronization. Today, prog...
Thomas F. Wenisch, Anastassia Ailamaki, Babak Fals...
ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
13 years 11 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
ISCA
1999
IEEE
104views Hardware» more  ISCA 1999»
13 years 9 months ago
Is SC + ILP=RC?
Sequential consistency (SC) is the simplest programming interface for shared-memory systems but imposes program order among all memory operations, possibly precluding high perform...
Chris Gniady, Babak Falsafi, T. N. Vijaykumar
ICCL
1998
IEEE
13 years 9 months ago
Transactions for Java
We present a design and implementation of transactions and general-purpose persistence for Java. These additions allow Java programmers to manipulate any Java object using transac...
Alex Garthwaite, Scott Nettles