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» Route Packets, Not Wires: On-Chip Interconnection Networks
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GLOBECOM
2006
IEEE
13 years 11 months ago
Scalable Layer-2/Layer-3 Multistage Switching Architectures for Software Routers
Abstract— Software routers are becoming an important alternative to proprietary and expensive network devices, because they exploit the economy of scale of the PC market and open...
Andrea Bianco, Jorge M. Finochietto, Giulio Galant...
ICPP
1990
IEEE
13 years 9 months ago
Interleaved All-to-All Reliable Broadcast on Meshes and Hypercubes
All-to-all (ATA) reliable broadcast is the problem of reliably distributing information from every node to every other node in point-to-point interconnection networks. A good solut...
Sunggu Lee, Kang G. Shin
ICDCSW
2008
IEEE
13 years 12 months ago
Fast Link Assessment in Wireless Mesh Networks by Using Non-Constant Weight Code
Abstract— The wireless mesh network is experiencing tremendous growth with the standardization of IEEE 802.11 and IEEE 802.16 technologies. Compared to its wired counterpart, the...
Ravi Nelavelli, Rajesh Prasad, Hongyi Wu
ICES
2010
Springer
277views Hardware» more  ICES 2010»
13 years 3 months ago
An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...
Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep...
DAC
2002
ACM
14 years 6 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...