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» Runlength Compression Techniques for FPGA Configurations
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ASPDAC
2004
ACM
218views Hardware» more  ASPDAC 2004»
13 years 10 months ago
A compressed frame buffer to reduce display power consumption in mobile systems
Abstract-- Despite the limited power available in a batteryoperated hand-held device, a display system must still have an enough resolution and sufficient color depth to deliver th...
Hojun Shim, Naehyuck Chang, Massoud Pedram
FPL
2006
Springer
96views Hardware» more  FPL 2006»
13 years 10 months ago
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
Allan Carroll, Carl Ebeling