17 search results - page 4 / 4 » S-Tree: a technique for buffered routing tree synthesis |
DAC
2011
ACM
12 years 5 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
ICCAD
1997
IEEE
13 years 10 months ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...