12 search results - page 2 / 3 » SACI: statistical static timing analysis of coupled intercon... |
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Shrinking feature sizes and process variations are of increasing concern in modern technology. It is urgent that we develop statistical interconnect timing models which are harmon...
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects. This effect is as significan...
CCGRID
2008
IEEE
13 years 6 months ago
2008
IEEE
Abstract--The current trend in high performance computing is to aggregate ever larger numbers of processing and interconnection elements in order to achieve desired levels of compu...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...