37 search results - page 2 / 8 » SCIMA-SMP: on-chip memory processor architecture for SMP |
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
MICRO
2005
IEEE
13 years 11 months ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
WMPI
2004
ACM
13 years 10 months ago
2004
ACM
Abstract. In this paper, we propose a processor architecture with programmable on-chip memory for a high-performance SMP (symmetric multi-processor) node named SCIMA-SMP (Software ...
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper explores generating efficient, portable HighSpeed Producer Consumer (HSPC) code on current shared memory architectures: Chip Multi-Processors (CMP), Simultaneous Multi...