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» SEU Mitigation Techniques for Microprocessor Control Logic
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DSD
2008
IEEE
136views Hardware» more  DSD 2008»
13 years 11 months ago
Network Interface Sharing Techniques for Area Optimized NoC Architectures
Although preliminary analysis frameworks point out the performance speed-ups achievable by on-chip networks with respect to state-of-the-art interconnects, the area concern remain...
Alberto Ferrante, Simone Medardoni, Davide Bertozz...
VTC
2010
IEEE
185views Communications» more  VTC 2010»
13 years 3 months ago
Fuzzy Logic Aided Dynamic Source Routing in Cross-Layer Operation Assisted Ad Hoc Networks
1The classic Dynamic Source Routing (DSR) protocol opts for the route requiring the lowest number of hops for transmitting data from the source to the destination. However, owing t...
Jing Zuo, Soon Xin Ng, Lajos Hanzo
ICCAD
2006
IEEE
169views Hardware» more  ICCAD 2006»
14 years 2 months ago
Microarchitecture parameter selection to optimize system performance under process variation
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
Xiaoyao Liang, David Brooks
TMC
2012
11 years 7 months ago
Fast Data Collection in Tree-Based Wireless Sensor Networks
—We investigate the following fundamental question—how fast can information be collected from a wireless sensor network organized as tree? To address this, we explore and evalu...
Özlem Durmaz Incel, Amitabha Ghosh, Bhaskar K...
ISCA
2012
IEEE
218views Hardware» more  ISCA 2012»
11 years 7 months ago
CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures
Wide SIMD-based GPUs have evolved into a promising platform for running general purpose workloads. Current programmable GPUs allow even code with irregular control to execute well...
Minsoo Rhu, Mattan Erez