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» SOI Transistor Model for Fast Transient Simulation
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ICCAD
2003
IEEE
115views Hardware» more  ICCAD 2003»
14 years 1 months ago
SOI Transistor Model for Fast Transient Simulation
D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Eg...
ICCAD
1999
IEEE
109views Hardware» more  ICCAD 1999»
13 years 9 months ago
Transient sensitivity computation for transistor level analysis and tuning
This paper presents a general method for computing transient sensitivities using both the direct and adjoint methods in event driven controlled explicit simulation algorithms that...
Tuyen V. Nguyen, Peter O'Brien, David W. Winston
ISLPED
1995
ACM
129views Hardware» more  ISLPED 1995»
13 years 8 months ago
CMOS dynamic power estimation based on collapsible current source transistor modeling
When estimating the dynamic power dissipated by a circuit di erent methods ranging from numeric analog simulation to event-driven logic simulation have been proposed. However, as ...
Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Pet...
DATE
2010
IEEE
122views Hardware» more  DATE 2010»
13 years 10 months ago
Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation
—This paper presents a modeling method for power distribution networks (PDNs) consisting of multilayered power/ground planes of the PCB/Package. Using our proposed method, multip...
Takayuki Watanabe, Hideki Asai
DAC
2008
ACM
14 years 5 months ago
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
S. Raja, F. Varadi, Murat R. Becer, Joao Geada