Sciweavers

393 search results - page 79 / 79
» SPAX: A New Parallel Processing System for Commercial Applic...
Sort
View
TVLSI
2008
108views more  TVLSI 2008»
13 years 5 months ago
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo de...
Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu
ICCD
2007
IEEE
195views Hardware» more  ICCD 2007»
13 years 9 months ago
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
Jugash Chandarlapati, Mainak Chaudhuri
ASPLOS
2006
ACM
13 years 9 months ago
Integrated network interfaces for high-bandwidth TCP/IP
This paper proposes new network interface controller (NIC) designs that take advantage of integration with the host CPU to provide increased flexibility for operating system kerne...
Nathan L. Binkert, Ali G. Saidi, Steven K. Reinhar...