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INTEGRATION
2008
87views more  INTEGRATION 2008»
13 years 5 months ago
SafeResynth: A new technique for physical synthesis
Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design,...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Safe Delay Optimization for Physical Synthesis
-- Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the final result, often by neg...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
DAC
2005
ACM
14 years 6 months ago
Incremental retiming for FPGA physical synthesis
In this paper, we present a new linear-time retiming algorithm that produces near-optimal results. Our implementation is specifically targeted at Altera's Stratix [1] FPGAbas...
Deshanand P. Singh, Valavan Manohararajah, Stephen...
SIGGRAPH
1999
ACM
13 years 9 months ago
A Perceptually Based Physical Error Metric for Realistic Image Synthesis
We introduce a new concept for accelerating realistic image synthesis algorithms. At the core of this procedure is a novel physical error metric that correctly predicts the percep...
Mahesh Ramasubramanian, Sumanta N. Pattanaik, Dona...
ICCAD
1998
IEEE
101views Hardware» more  ICCAD 1998»
13 years 9 months ago
Wireplanning in logic synthesis
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deepsubmicron technologies. We first show that conv...
Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alb...