Sciweavers

2 search results - page 1 / 1
» Scalable Hardware-Algorithms for Binary Prefix Sums
Sort
View
IPPS
1999
IEEE
13 years 8 months ago
Scalable Hardware-Algorithms for Binary Prefix Sums
Abstract. Themain contributionof thiswork isto propose a numberof broadcastefficient VLSI architectures for computing the sum and the prefix sums of a w k-bit, k 2, binary sequenc...
Rong Lin, Koji Nakano, Stephan Olariu, Maria Crist...
IPPS
1998
IEEE
13 years 8 months ago
A Scalable VLSI Architecture for Binary Prefix Sums
The task of computingbinary prefix sums (BPS, for short) arises, for example, in expression evaluation, data and storage compaction, and routing. This paper describes a scalable V...
Rong Lin, Koji Nakano, Stephan Olariu, Maria Crist...