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FPGA
2004
ACM
163views FPGA» more  FPGA 2004»
13 years 9 months ago
Time and area efficient pattern matching on FPGAs
Pattern matching for network security and intrusion detection demands exceptionally high performance. Much work has been done in this field, and yet there is still significant roo...
Zachary K. Baker, Viktor K. Prasanna
IPPS
2008
IEEE
14 years 1 days ago
Energy efficient packet classification hardware accelerator
Packet classification is an important function in a router’s line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classifi...
Alan Kennedy, Xiaojun Wang, Bin Liu
CAL
2008
13 years 5 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
ALGORITHMICA
2006
77views more  ALGORITHMICA 2006»
13 years 5 months ago
Scalable Parallel Algorithms for FPT Problems
Algorithmic methods based on the theory of fixed-parameter tractability are combined with powerful computational platforms to launch systematic attacks on combinatorial problems o...
Faisal N. Abu-Khzam, Michael A. Langston, Pushkar ...
GLOBECOM
2009
IEEE
13 years 9 months ago
Energy-Efficient Multi-Pipeline Architecture for Terabit Packet Classification
Energy efficiency has become a critical concern in designing high speed packet classification engines for next generation routers. Although TCAM-based solutions can provide high th...
Weirong Jiang, Viktor K. Prasanna