2057 search results - page 2 / 412 » Scalable and Structured Scheduling |
ISCA
2012
IEEE
11 years 8 months ago
2012
IEEE
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
ICMCS
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper addresses the problem of optimizing the playback delay experienced by a population of heterogeneous clients, in video streaming applications. We consider a typical broa...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
INFOCOM
2000
IEEE
13 years 10 months ago
2000
IEEE
-In this paper, we present a fast and scalable pipelined priority queue architecture for use in high-performance switches with support for fine-grained quality of service (QoS) gu...
IPPS
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...