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» Scaling, Power and the Future of CMOS
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DT
2006
109views more  DT 2006»
13 years 5 months ago
Test Consideration for Nanometer-Scale CMOS Circuits
The ITRS (International Technology Roadmap for Semiconductors) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing de...
Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng
ISCAS
2007
IEEE
113views Hardware» more  ISCAS 2007»
14 years 19 hour ago
Design Considerations for Future RF Circuits
TheRFdesignparadigm will changesignificantly asCMOS technology scales and integration levels rise to accommodate multi-band, multi-mode transceivers and baseband processors. This...
Behzad Razavi
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
13 years 11 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
Sanjeev K. Jain, Pankaj Agarwal
TVLSI
2002
93views more  TVLSI 2002»
13 years 5 months ago
Simultaneous switching noise in on-chip CMOS power distribution networks
Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra lar...
Kevin T. Tang, Eby G. Friedman
DATE
2010
IEEE
148views Hardware» more  DATE 2010»
13 years 10 months ago
Scalable stochastic processors
Abstract—Future microprocessors increasingly rely on an unreliable CMOS fabric due to aggressive scaling of voltage and frequency, and shrinking design margins. Fortunately, many...
Sriram Narayanan, John Sartori, Rakesh Kumar, Doug...