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2006
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A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology

10 years 3 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has approached the limit when direct tunneling causes gate leakage in both on state and off state of MOSFET transistor operation modes. Also, lower operating voltage will lower the stability of SRAM cell resulting in lower value of static noise margin. In this paper, a novel read ‘0’ static noise margin (SNM) free eight transistors (8T) SRAM cell is proposed that reduces gate leakage power in the zero state, taking into consideration the fact that in ordinary program most of the bits stored in caches are zeros for both the data and instruction streams. Compared to conventional six transistors (6T) SRAM cell, new 8T SRAM cell reduces total leakage by 50.2% in the zero state at low temperature, where gate leakage is dominant. High VT transistors in 8T SRAM cell can be used to further reduce both gate and sub thresho...
Sanjeev K. Jain, Pankaj Agarwal
Added 12 Jun 2010
Updated 12 Jun 2010
Type Conference
Year 2006
Where VLSID
Authors Sanjeev K. Jain, Pankaj Agarwal
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