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» Scaling IP Routing with the Core Router-Integrated Overlay
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INFOCOM
2008
IEEE
13 years 11 months ago
Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup
—Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of toda...
Weirong Jiang, Qingbo Wang, Viktor K. Prasanna
INFOCOM
2005
IEEE
13 years 11 months ago
Practical routing-layer support for scalable multihoming
— The recent trend of rapid increase in routing table sizes at routers comprising the Internet’s core is posing a serious challenge to the current Internet’s scalability, ava...
Ramakrishna Gummadi, Ramesh Govindan
CISIS
2009
IEEE
14 years 4 days ago
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
Francisco Gilabert Villamón, Daniele Ludovi...
IEEEPACT
2003
IEEE
13 years 10 months ago
Memory Hierarchy Design for a Multiprocessor Look-up Engine
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the numb...
Jean-Loup Baer, Douglas Low, Patrick Crowley, Neal...
SBCCI
2005
ACM
114views VLSI» more  SBCCI 2005»
13 years 11 months ago
Traffic generation and performance evaluation for mesh-based NoCs
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...