2 search results - page 1 / 1 » Scaling VLSI design debugging with interpolation |
FMCAD
2009
Springer
13 years 11 months ago
2009
Springer
—Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design ...
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
The continuing VLSI technology scaling leads to increasingly significant power supply fluctuations, which need to be modeled accurately in circuit design and verification. Meanwhi...