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» Scaling the issue window with look-ahead latency prediction
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IJCAI
2003
13 years 6 months ago
Learning Value Predictors for the Speculative Execution of Information Gathering Plans
Speculative execution of information gathering plans can dramatically reduce the effect of source I/O latencies on overall performance. However, the utility of speculation is clos...
Greg Barish, Craig A. Knoblock
ISCA
1998
IEEE
125views Hardware» more  ISCA 1998»
13 years 9 months ago
Performance Characterization of a Quad Pentium Pro SMP using OLTP Workloads
Commercial applications are an important, yet often overlooked, workload with significantly different characteristics from technical workloads. The potential impact of these diffe...
Kimberly Keeton, David A. Patterson, Yong Qiang He...
IPPS
2007
IEEE
13 years 11 months ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...
ASPDAC
2009
ACM
145views Hardware» more  ASPDAC 2009»
13 years 12 months ago
High performance on-chip differential signaling using passive compensation for global communication
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines is pr...
Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori ...
CJ
2006
84views more  CJ 2006»
13 years 5 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope